.SUBCKT mcr8sn anode gate cathode PARAMS: ************************************** * Model Generated by CZ LAB * * August 27, 2001 * * Copyright(c) On Semiconductor * * All Rights Reserved * *Commercial Use or Resale Restricted * ************************************** *Silicon Controlled Rectifier *MODEL FORMAT: PSpice + Vdrm=960v Vrrm=960v Idrm=10u + Ih=0.5ma dVdt=1.5e7 + Igt=0.025ma Vgt=0.7v * Vgt must be greater than 0.65 + Vtm=1.25v Itm=16 + Ton=2u Toff=15u * Where: * Vdrm => Forward breakover voltage * Vrrm => Reverse breakdown voltage * Idrm => Peak blocking current * Ih => Holding current * dVdt => Critical value for dV/dt triggering * Igt => Gate trigger current * Vgt => Gate trigger voltage * Vtm => On-state voltage * Itm => On-state current * Ton => Turn-on time * Toff => Turn-off time *------------------------------------------------------------------------------- * Library of Thyristor (SCR and Triac) models * This is a reduced version of MicroSim's Thyristor components library. * You are welcome to make as many copies of it as you find convenient. * Library of SCR models * NOTE: This library requires the "Analog Behavioral Modeling" * option available with PSpice. A model developed without * Behavioral Modeling was found to be very slow and not * very robust. * This macromodel uses a controlled switch as the basic SCR * structure. In all cases, the designer should use * the manufacturer's data book for actual part selection. * The required parameters were derived from data sheet (Motorola) * information on each part. When available, only "typical" * parameters are used (except for Idrm which is always * a "max" value). If a "typical" parameter is not available, * a "min" or "max" value may be used in which case a comment is * made in the library. * The SCRs are modeled at room temperature and do not track * changes with temperature. Note that Vdrm is specified by the * manufacturer as valid over a temperature range. Also, in * nearly all cases, dVdt and Toff are specified by the * manufacturer at approximately 100 degrees C. This results in a * model which is somewhat "conservative" for a room temperature * model. * The parameter dVdt (when available from the date sheet) is used * to model the Critical Rate of Rise of Off-State Voltage. If * not specified, dVdt is defaulted to 1000 V/microsecond. * A side effect of this model is that the turn-on current, Ion, * is determined by Vtm/(Ih*Vdrm). Vtm is also used as the * holding voltage. * Main conduction path Scr anode anode0 control 0 Vswitch ; controlled switch Dak1 anode0 anode2 Dakfwd OFF ; SCR is initially off Dka cathode anode0 Dkarev OFF VIak anode2 cathode ; current sensor * dVdt Turn-on Emon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000) CdVdt dvdt0 dvdt1 100pfd ; displacement current Rdlay dvdt1 dvdt2 1k VdVdt dvdt2 cathode DC 0.0 EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10) RdVdt condvdt 0 1meg * Gate Rseries gate gate1 {(Vgt-0.65)/Igt} Rshunt gate1 gate2 {0.65/Igt} Dgkf gate1 gate2 Dgk VIgf gate2 cathode ; current sensor * Gate Turn-on Egate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10) Rgate1 gate4 0 1meg Egon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10) Rgon1 congate 0 1meg * Main Turn-on EItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000) RItot Itot 0 1meg Eprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1) Rprod prod 0 1meg Elin conmain 0 TABLE + {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10) Rlin conmain 0 1meg * Turn-on/Turn-off control Eonoff contot 0 TABLE + {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10) * Turn-on/Turn-off delays Rton contot dlay1 825 Dton dlay1 control Delay Rtoff contot dlay2 {290*Toff/Ton} Dtoff control dlay2 Delay Cton control 0 {Ton/454} * Reverse breakdown Dbreak anode break1 Dbreak Dbreak2 cathode break1 Dseries * Controlled switch model .MODEL Vswitch vswitch + (Ron = {(Vtm-0.7)/Itm}, Roff = {Vdrm*Vdrm/(Vtm*Ih)}, + Von = 5.0, Voff = 1.5) * Diodes .MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5) .MODEL Dseries D (Is=1E-14) .MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01) .MODEL Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01) .MODEL Dakfwd D (Is=4E-11 Cjo=5pf) .MODEL Dbreak D (Ibv=1E-7 Bv={1.1*Vrrm} Cjo=5pf Rs=0.5) * Allow the gate to float if required Rfloat gate cathode 1e10 .ENDS *$